DC Line Model: CHVDC2

Following checks and corrections are applied during Validation and AutoCorrection.

• If 0.0 < Tr < 0.5*Mult*TimeStep then Ts = 0, ElseIf 0.5*Mult*TimeStep < Tr < Mult*TimeStep then Tr = Mult*TimeStep
  (same done for Tref, Tmax, Tur, Tdr, Tui, Tdi, and Tram)
• If Tvd < Mult*TimeStep then Tvd = Mult*TimeStep
• If rmax< rmin then swap the values. If rmax < 0 then rmax change sign to positive. If rmin > 0 then change sign to negative.
  (same is done for max_err and min_err)

Mult represents the user-specified value Minimum time constant size as multiple of time step option on the Validation page of the Transient Stability Dialog

TimeStep represents the integration time step being used as described on TimeStep

Following treatment is handled during the transient numerical simulation

• if Vac_ref is larger than either the initial inverter bus or rectifier bus ac per unit voltage and the AC VDCOL is active, then Vac_ref will be modified to be equal to the minimum of these two values.
• If the natural frequency of the RLC circuit formed by DC circuit is to large, then this would result in numerical problems. To prevent this, the capacitance of the DC line will be ignored.
• if either Talpr and Talpi are less than 2*TimeStep, then they are changed to be equal to 2*TimeStep.